Why is Libera Hadron a guaranty for a safe decision?

• GSI upgraded the SIS18 ring with Libera Hadron
• GSI and CERN participated actively in the Libera development

ALL-IN-ONE

• Fully digital all-in-one solution
• It enables customizable real-time digital signal processing and data storage 
• Highly configurable triggering mechanism

CUSTOMIZABLE

• Using the Libera field programmable gate array (FPGA) building blocks that interface with the hardware, it is possible to customize the product to your specific needs

Easy to integrate in the control system

• The Libera high-level software library (CSPI) separates control-system specific knowledge from low level details and logic related to a Libera processor.

Performance Specifications

Parameter	Value
Sampling frequency fs	125MHz ±90ppm (VCXO)
ADC granularity	14 bit
Maximum amplitude per input	2.0 Vpp
FPGA size and speed grade	XC2VP30FG1152-6
Memory size	DDR2RAM 128 MB
Input analog bandwidth	100 kHz-250 MHz

Libera Hadron data paths
The data from four ADCs is processed in the DSP block. This is the only accelerator dependent block and is therefore customized. Resulting data is stored in the deep history buffer. Raw data can be stored, too. The data from history buffer can be easily retrieved by the control system.