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Libera Workshop





The Libera Workshop is an opportunity to network with experts from the accelerator field and explore how to optimize the beam stability from injection to the end station.

 

The participants learn about the use of Libera instruments at different accelerators around the world and get practical experience as well as intensive training. The workshop focuses on applications using the Libera family of instruments, state-of-the-art instrumentation systems used for diagnostics and beam stabilization at particle accelerators.

 

GDX Module




Add GDX (Gigabit Data eXchange) Module to your Libera Brilliance+ and build the fast global orbit feedback!


Libera Brilliance+ with GDX Module implemented provides:

  • Local and global fast acquisition data concentration
  • Fast acquisition history buffer storage
  • Global orbit correction algorithm
  • Fast acquisition output stream
  • Magnet corrector power supply output stream
  • Adjustable data rate and bandwidth


These features provide a complete low-jitter, high-availability FOFB solution, implemented entirely on the FPGA. It can interface directly with the power supplies of the corrector magnets.

Data concentration can be carried out using the Libera Grouping or the user written protocol.

GDX Module features:

  • Virtex 6 series of Xilinx FPGA, speed grade 2 (default), 6.5 Gbps
  • DDR3 memory
  • Protocol independent SFP slots (4)
  • Low latency high speed LVDS links to processor modules
  • FPGA development kit





Add GDX (Gigabit Data eXchange) Module to your Libera Brilliance+ and build the fast global orbit feedback!



Libera Brilliance+ with GDX Module implemented provides:

  • Local and global fast acquisition data concentration
  • Fast acquisition history buffer storage
  • Global orbit correction algorithm
  • Fast acquisition output stream
  • Magnet corrector power supply output stream
  • Adjustable data rate and bandwidth

These features provide a complete low-jitter, high-availability FOFB solution, implemented entirely on the FPGA. It can interface directly with the power supplies of the corrector magnets.

Data concentration can be carried out using the Libera Grouping or the user written protocol.

GDX Module features:

  • Virtex 6 series of Xilinx FPGA, speed grade 2 (default), 6.5 Gbps
  • DDR3 memory
  • Protocol independent SFP slots (4)
  • Low latency high speed LVDS links to processor modules
  • FPGA development kit

 

 







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